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Effect Of Body Biasing On 0.13 Um CMOS Transistor
Author(s) -
Noorfazila Kamal,
Nadhira Mohamad Fauzi
Publication year - 2019
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.b7817.129219
Subject(s) - pmos logic , nmos logic , biasing , cmos , mosfet , materials science , threshold voltage , transistor , electrical engineering , optoelectronics , field effect transistor , electronic engineering , voltage , engineering
Complementary metal-oxide semiconductor (CMOS) consist of n-type metal-oxide semiconductor field effect transistor (NMOS) and p-type MOSFET (PMOS). In common practice, only three terminals of these transistors are used, namely gate, source and drain. Meanwhile, the fourth terminal, which is body terminal is tied to source. Changing body terminal bias causes the transistor to have a body effect. In this work, optimum body biasing for 0.13 µm NMOS and PMOS are identified. Effect of body biasing to the MOSFETs are investigated. In addition, how body biases affect CMOS circuits are also observed. Three type of body biasing are considered, namely Forward Body Biasing (FBB), Reverse Body Biasing (RBB), and Dynamic Threshold MOS (DTMOS). Drain current, Id versus gate voltage, VG and drain current, Id versus drain-source voltage, VDS for FBB, RBB and DTMOS are simulated to determine the optimum operating point for each biasing technique. To observe the effect of body biasing techniques on the circuits, inverter and common source amplifier are constructed using FBB, RBB and DTMOS. In addition, the circuits also constructed in zero body biasing (ZBB) for comparison. The results show that, optimum body biasing is at 0.6 V for all three body biasing techniques. FBB and DTMOS cause the threshold voltage, Vth to decrease but increase the leakage current. On the other hand, RBB causes increase in threshold voltage, Vth yet reduces the leakage current of the CMOS. The results obtained in this work will enable other circuit designers to determine the optimum FBB, RBB and DTMOS operating point.

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