Open AccessPerformance Analysis of Karatsuba Vedic Multiplier and Computation Sharing Multiplier in the Adaptive Filter Design
Author(s) -
Madhavan Swaminathan,
Dr.Sasikala Subramaniyam,
Dr.G. Murugesan
Publication year - 2019
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.b7454.129219
Subject(s) - multiplier (economics) , adaptive filter , very large scale integration , kernel adaptive filter , digital signal processing , computer science , field programmable gate array , digital filter , adder , electronic engineering , computation , filter (signal processing) , digital signal processor , filter design , arithmetic , signal processing , algorithm , mathematics , computer hardware , embedded system , cmos , engineering , economics , computer vision , macroeconomics
As real time signals change continuously, adaptive filtering is required for noise cancellation. An adaptive filter is one whose characteristics can be modified by adjusting its parameters according to an optimization algorithm The adaptive filtering operations can be implemented as a sequence of logic operations on a Digital Signal Processing (DSP) chip,Gate Arrays such as FPGA or Application Specific Integrated Circuits. There is always a tradeoff in the parameters area, power and speed in VLSI. This paper provides the implementation of adaptive LMS Filter using different types of multiplier and its analysis for the various parameters. The LMS Filter is designed using conventional array multiplier, Computation Sharing Mutliplier(CSHM) and Karatsuba Vedic Multiplier. The results show 70% reduction in delay and 19% reduction in area on using Karatsuba Vedic Multiplier ofr adaptive filter design.