Full Adders using GDI (With Full Swing) Technique for Power Efficient Computing | Zendy

M. Lakshmana Kumar | Zendy; M. Aditya | Zendy; Degala Kavya Vineela | Zendy; Battini Ramesh Reddy | Zendy; B. Lakshmi | Zendy; Kudikyala Bhargavi | Zendy

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Full Adders using GDI (With Full Swing) Technique for Power Efficient Computing

Author(s) -

M. Lakshmana Kumar,

M. Aditya,

Degala Kavya Vineela,

Battini Ramesh Reddy,

B. Lakshmi,

Kudikyala Bhargavi

Publication year - 2019

Publication title -

international journal of innovative technology and exploring engineering

Language(s) - English

Resource type - Journals

ISSN - 2278-3075

DOI - 10.35940/ijitee.b6651.129219

Subject(s) - adder , multiplexer , computer science , electronic circuit , carry save adder , electronic engineering , power–delay product , subtraction , computer hardware , power (physics) , graphics , digital signal processing , cmos , arithmetic , multiplexing , electrical engineering , engineering , mathematics , telecommunications , physics , quantum mechanics , computer graphics (images)

Adders, Multiplexers and other arithmetic circuits have a crucial role in Digital Signal Processing and various real time applications. Among those, Full adder is a central for most of the digital operations that perform subtraction or addition. Major component is Adder with High performance and a power efficient in specific applications. In this paper, the adder with high performance and power efficient are designed using Gate Diffusion Logic which reduces threshold voltage problem. We designed the circuits with minimum power consumption and with high performance efficiency. For the simulation of the circuits Mentor Graphics with 130nm technology is used. The obtained result shows that the proposed designs consume the minimum power when compared to other designs which are taken for the comparison.

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