Open AccessDesign Environment for Verilog Module Analysis using Open Source Tools
Publication year - 2019
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.b1069.1292s19
Subject(s) - verilog , reusability , computer science , scalability , reliability (semiconductor) , network on a chip , routing (electronic design automation) , design for manufacturability , embedded system , computer architecture , chip , transistor , field programmable gate array , telecommunications , engineering , electrical engineering , software , operating system , power (physics) , physics , quantum mechanics , voltage
Network-on-Chip provides possible solutions for the limitations and challenges by the present day architectures for the interconnections. The characteristics of NoCs include energy efficiency, reliability, scalability, reusability and distributed routing decisions. The existence of today’s semiconductor industry depends on shorter time-to-market, challenge of meeting increasing transistor density, reduced product life cycle, and operating frequencies getting higher. This paper discusses about a design environment for the analysis of Verilog NoC module. Tools such as Icarus Verilog, GTK Wave, Yosys etc. which are used for compilation, simulation and synthesis of the NoC are also discussed in this paper.