Open AccessLow Voltage CMOS Power Amplifier with Integrated Capacitive Harmonic Termination
Author(s) -
Sureshkumar Subramian*,
Jagadheswaran Rajendran,
Sofiyah Sal Hamid,
Arvind Singh Rawat
Publication year - 2019
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.a5021.129219
Subject(s) - amplifier , electrical engineering , cmos , capacitive sensing , linearity , total harmonic distortion , voltage , bandwidth (computing) , harmonic , power added efficiency , materials science , rf power amplifier , electronic engineering , engineering , telecommunications , physics , acoustics
This paper presents a novel design methodology to improve the power added efficiency (PAE) for a CMOS power amplifier (PA), qualifying it for low voltage mobile wireless communications such as the NB-IoT. The capacitive harmonic termination (CHT) integrated at the output of the main stage PA to minimise the effect of the second harmonic distortion in order to improve the PAE. The CHT PA able to deliver a PAE of 40% at drain voltage of 3.3 V from 1.9 GHz - 2.1 GHz. The corresponding power gain is 14 dB for 200 MHz bandwidth. The achieved third-order intercept point (OIP3) is 33 dBm, which serves as a proof that the CHT technique has a minimal trade-off to the linearity performance of the PA.