Open AccessArea Optimization using Structural Modeling for Gate Level Implementation of SPI for Microcontroller
Author(s) -
Amrut Anilrao Purohit*,
Mohammed Riyaz Ahmed
Publication year - 2019
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.a4588.119119
Subject(s) - universal asynchronous receiver/transmitter , computer science , embedded system , verilog , microcontroller , asynchronous communication , interface (matter) , electronics , miniaturization , transmitter , computer hardware , chip , field programmable gate array , electrical engineering , engineering , telecommunications , channel (broadcasting) , bubble , maximum bubble pressure method , parallel computing
The need for miniaturization has been the driving force in chip manufacturing. The proliferation of IoT, robotics, consumer electronics and medical instruments pose unprecedented demands on the embedded system design. The area optimization can be achieved either by reducing the size of transistors or by optimizing (reducing) the circuit at the gate level. The first solution has attracted many researchers while the later has not been explored to its full potential. The aim is to design a System on Chip (SoC) to satisfy the dynamic requirements of disruptive technologies while occupying the lesser area. The design and testing of communication interfaces such as Serial Peripheral Interface (SPI), Inter-IC Communication (I2C), Universal Asynchronous Receiver and Transmitter (UART) are very crucial in the area optimization of microcontroller design. Since SPI being an important communication protocol, this work reports the preliminary research carried in the design and verification of it. In this work, Verilog is used for the design and verification of the SPI module. The results show that there is a drastic reduction in the number of Look-Up-Tables (LUTs) and slices required to build the circuit. We conclude that sophisticated optimization techniques of the circuit at the gate level has the potential to reduce the area by half.