Open AccessImplementation of VLSI Architecture for Montgomery Modular Multiplier
Author(s) -
M.V. Priya,
R. Priyanka,
T. Manikandan,
Segun Joshua,
Sushil Kumar
Publication year - 2019
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.a1045.1191s19
Subject(s) - adder , schematic , computer science , cmos , very large scale integration , multiplier (economics) , modular design , arithmetic , carry save adder , computer hardware , embedded system , electronic engineering , mathematics , engineering , economics , macroeconomics , operating system
The paper proposes a Montgomery Modular Multiplier (MMM) using a simple and efficient Montgomery multiplication algorithm. Here a modification in the form of using hybrid full adders in the Carry Save adder is proposed. The hybrid full adder is designed using a conventional Complementary Metal Oxide Semiconductor and transmission gate logic. There is about 54% and 55% reduction of area (no. of components) in Radix 2 MMM and Semi-Carry-Save (SCS) based MMM with hybrid full adders. There is significant reduction in the power dissipation of 52% for Radix 2 MMM and 46% of SCS based MMM when hybrid adders are used instead of C-CMOS Full-Adders. The delay is also reduced by 47% in SCS based MMM as compared to that of Radix 2 MMM. The software used are Xilinx ISE 14.2 and Mentor Graphics Pyxis Schematic in 180-nm technology.