Open AccessDesign of Test Pattern Generator for Testing Crosstalk Faults in TSVs
Author(s) -
Praveen Kona,
K. Ashoka Reddy,
R. Parthasarathy
Publication year - 2019
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.a1001.1191s19
Subject(s) - crosstalk , digital pattern generator , verilog , automatic test pattern generation , computer science , integrated circuit , electronic engineering , engineering , electronic circuit , embedded system , electrical engineering , field programmable gate array
Design of Test pattern generator to test crosstalk faults in Through Silicon Vias (TSV) in three dimensional integrated circuits presented in this paper. A well-known test pattern generation model for testing crosstalk called as Maximum aggressor fault model is adopted in the design. The finite state machine diagram for design of TPG presented in reference [1] is modified and the complete design of TPG is discussed in this paper. Verilog HDL Simulation and synthesis results of the proposed Test pattern generator is discussed.