Open AccessClock Tree Optimization for Multi-Corner Multi-Mode Timing Closure with Different Design Flows
Author(s) -
Kasi Annapurna. Nalluri,
G. Janardhana Raju
Publication year - 2019
Publication title -
international journal of engineering and advanced technology
Language(s) - English
Resource type - Journals
ISSN - 2249-8958
DOI - 10.35940/ijeat.f8924.088619
Subject(s) - clock gating , cpu multiplier , clock network , clock skew , clock domain crossing , digital clock manager , timing failure , computer science , clock signal , electronic engineering , tree (set theory) , synchronous circuit , static timing analysis , clock synchronization , embedded system , engineering , synchronization (alternating current) , channel (broadcasting) , jitter , mathematics , telecommunications , mathematical analysis
Clock Tree Optimization for Multi Corner Multi Mode Timing closure is done with Integrated Clock Gating cells. It is power efficient clock tree technique because, it will reduce the switching power usage of clock. It is implemented using integrated clock Gating cells for reducing the switching power caused by clock propagation in the design during Clock Tree Synthesis. The multi mode and multi corner uses integrated clock gating cells to achieve timing and these cells will reduce dynamic power .This technique can be applied to industrial Digital Intellectual Property(DIP). The cells used in the design are fabricated by using 22nm FDSOI process and these cells used as clock pins by Automatic Root Clock Pin (ARCP) in Clock Specification file during clock tree synthesis along with proposed flows for reducing buffer count. The result shows that the number of buffers added in the each stage is reduced by the proposed flow and also we achieve the timing, power and area. In this paper, by using clock tree optimization technique the clock power dissipation in the chip is reduced by Integrated clock gating cells.