Open AccessEffective Usage of Chip Area by Optimizing the Dead Space
Author(s) -
Ganugaphati Venkata Sai Mohan*,
Venkat Rao Ganjanaboyina
Publication year - 2019
Publication title -
international journal of engineering and advanced technology
Language(s) - English
Resource type - Journals
ISSN - 2249-8958
DOI - 10.35940/ijeat.f8753.088619
Subject(s) - floor plan , very large scale integration , computer science , plan (archaeology) , dead zone , interconnection , chip , cadence , physical design , space (punctuation) , placement , computer engineering , embedded system , circuit design , engineering drawing , electronic engineering , engineering , telecommunications , operating system , oceanography , archaeology , history , geology
In the modern VLSI (Very Large Scale Integration) physical design, floor plan is the main step to optimize the circuit. The objective of floor plan is to optimize the interconnection between modules, area optimization and minimize the dead space. For very deep micron technologies, one of the major issue to design an chip is Dead space in physical design. In this paper, we introduced an algorithm for reducing dead space. This algorithm wrote in tickel programming language and implemented in Cadence Innovas Encounter Tool. By comparing to default algorithm floor plan, this algorithm reduces more dead space in the floor plan stage of the design.