Open AccessDesign and Performance Analysis of Hybrid Full Adder using Fin FET 40nm Technology
Author(s) -
Palakurthi Sreekanth,
K. Sri Rama Krishna,
Sadulla Shaik
Publication year - 2019
Publication title -
international journal of engineering and advanced technology
Language(s) - English
Resource type - Journals
ISSN - 2249-8958
DOI - 10.35940/ijeat.f8053.088619
Subject(s) - adder , cmos , power–delay product , electronic engineering , cadence , transistor , computer science , propagation delay , power consumption , electronic circuit , electrical engineering , power (physics) , engineering , voltage , physics , quantum mechanics
Designing a low power and energy efficient circuits in FinFET technology is of great Challenge. This paper presents the internal logic structure and circuit operation using the devices, CMOS and FinFETs for designing the hybrid adder cells. At transistor level, CMOS and FinFET based hybrid full adder (HFA) and improved hybrid full adder (IHFA) is designed. Simulations are carried out using the cadence tool in UMC 40nm and the performance analysis of these HFA and IHFA are compared with the 40nm FinFET technology. It is observed that IHFA is better when compared with the HFA in terms of propagation delay, power consumption and energy delay product. IHFA achieves the higher drive current and low leakage power for better mobility and transistor scaling as compared with HFA.