Open AccessDesign and Implementation of Kogge Stone adder using CMOS and GDI Design: VLSI Based
Author(s) -
Dr.S.Vasantha swaminathan,
J. Surendiran,
B.P.Pradeep Kumar
Publication year - 2019
Publication title -
international journal of engineering and advanced technology
Language(s) - English
Resource type - Journals
ISSN - 2249-8958
DOI - 10.35940/ijeat.f1422.0986s319
Subject(s) - adder , very large scale integration , cmos , computer science , prefix , transistor , computer hardware , cadence , arithmetic , computer architecture , parallel computing , electronic engineering , electrical engineering , embedded system , engineering , mathematics , linguistics , philosophy , voltage
Adders is a significant part in different math legitimate activity. Parallel Prefix Adder was developed as the most basic and effective circuit for double expansion. The Particular structure and execution are alluring for VLSI usage. In these papers, I can depict the structure and execution of the Kogge Stone Parallel Prefix Adders and actualized utilizing diverse plan procedure. CMOS (Complementary Metal Oxide Semiconductor) and GDI (Gate Diffusion Input) are the distinctive structure system utilized. . The plan and reenactment of rationale entryways is performed on CADENCE Design Suit 6.1.6 utilizing virtuoso and ADE Environment at GPDK 180nm innovation. The execution estimation considered for the presentation of the KSA is delay, number of door check/Transistor Count (territory) and power. Recreation reads are accomplished for 4-piece, 8-piece and 16-piece input information