Open AccessOptimization of CSA for Low Power and High-Speed using MTCMOS and GDI Techniques
Author(s) -
Tulasi Radhika Patnala,
Sankararao Majji,
Gopala Krishna Pasumarthi
Publication year - 2019
Publication title -
international journal of engineering and advanced technology
Language(s) - English
Resource type - Journals
ISSN - 2249-8958
DOI - 10.35940/ijeat.e1062.0785s319
Subject(s) - adder , power–delay product , computer science , electronic engineering , power (physics) , reliability (semiconductor) , digital signal processing , cmos , cadence , computer hardware , embedded system , engineering , physics , quantum mechanics
The basic operation involved in any analog, digital, control system, DSP’s is addition. Performance and reliability of almost every digital system is depends on performance of adder. Over the decade, many adder architectures are proposed and still research work is going on adder to obtain the best results in power, delay and power delay product (PDP). In this paper we proposed one of the fastest adder architecture called Carry Select adder (CSA) and optimization is done for performance parameters like delay and power using GDI (Gate Diffused Input) and MTCMOS techniques. Implementation has been done in standard gpdk 90nm technology using Cadence tool.