Open AccessDesign and Interfacing of I2C Master with Register and LCD Slaves
Author(s) -
A.Sainath Chaithanya,
D. Sindhuja,
D. Bhavana,
P. Vennela
Publication year - 2020
Publication title -
international journal of engineering and advanced technology
Language(s) - English
Resource type - Journals
ISSN - 2249-8958
DOI - 10.35940/ijeat.d7901.049420
Subject(s) - interfacing , verilog , computer science , computer hardware , embedded system , field programmable gate array
One of the foremost, well-liked, less sophisticated Serial communication standards, I2C; a bus protocol familiarly meant for the exchange of information among the peripherals residing on the constant circuit card, houses two-wires i.e., data and clock for supporting duplex communication between multiple masters and slaves do considered as prominent and efficient in Data transmission. The present work emphasizes on the I2C controller designed for interfacing with slaves, a simple control register of I2C switches/card where the data is written or scan from, subsequently, I2C core implementation on Spartan 3E FPGA, where one of its on-chip peripheral, in this case LCD treated as a slave for performing data transactions. The entire module is designed in Verilog HDL, functional checking is accomplished with the ISIM 10.0b simulator, followed by the design synthesis using Xilinx ISE14.4 tool