Open AccessFPGA Implementation of Fault Tolerant Adder using Verilog for High Speed VLSI Architectures
Author(s) -
Somashekhar,
Vikas Maheshwari,
R. P. Singh
Publication year - 2020
Publication title -
international journal of engineering and advanced technology
Language(s) - English
Resource type - Journals
ISSN - 2249-8958
DOI - 10.35940/ijeat.d7062.049420
Subject(s) - adder , verilog , computer science , field programmable gate array , very large scale integration , block (permutation group theory) , computer hardware , carry save adder , parallel computing , embedded system , chip , fault tolerance , computer architecture , mathematics , telecommunications , latency (audio) , distributed computing , geometry
The main objective is to detect and reduce the faults in full adder design using self checking and self repairing adder block. The rate of chip failure is directly proportional to chip density. This fault tolerant adder has high speed (Delay is 6.236ns) & implemented on FPGA Spartan 3 using XC3S50 device. The source code is written in verilog. In this design faults are identified and repaired using self checking and self repairing full adder methodologies.