Open AccessLow Complexity FFT Factorization for CS Reconstruction
Author(s) -
Alahari Radhika,
K. Satya Prasad,
K. Kishan Rao
Publication year - 2020
Publication title -
international journal of engineering and advanced technology
Language(s) - English
Resource type - Journals
ISSN - 2249-8958
DOI - 10.35940/ijeat.c4675.029320
Subject(s) - fast fourier transform , computer science , twiddle factor , matching pursuit , computational complexity theory , normalization (sociology) , computation , overhead (engineering) , algorithm , matrix multiplication , prime factor fft algorithm , field programmable gate array , parallel computing , computer engineering , compressed sensing , fourier transform , computer hardware , mathematics , fractional fourier transform , fourier analysis , mathematical analysis , physics , short time fourier transform , quantum mechanics , sociology , anthropology , quantum , operating system
In this paper is presented a novel area efficient Fast Fourier transform (FFT) for real-time compressive sensing (CS) reconstruction. Among various methodologies used for CS reconstruction algorithms, Greedy-based orthogonal matching pursuit (OMP) approach provides better solution in terms of accurate implementation with complex computations overhead. Several computationally intensive arithmetic operations like complex matrix multiplication are required to formulate correlative vectors making this algorithm highly complex and power consuming hardware implementation. Computational complexity becomes very important especially in complex FFT models to meet different operational standards and system requirements. In general, for real time applications, FFT transforms are required for high speed computations as well as with least possible complexity overhead in order to support wide range of applications. This paper presents an hardware efficient FFT computation technique with twiddle factor normalization for correlation optimization in orthogonal matching pursuit (OMP). Experimental results are provided to validate the performance metrics of the proposed normalization techniques against complexity and energy related issues. The proposed method is verified by FPGA synthesizer, and validated with appropriate currently available comparative analyzes.