Open AccessImplementation of 2D-DCT as an Efficient Accelerator for HEVC Video CODEC
Author(s) -
S Sumalatha.,
Rajeswari
Publication year - 2019
Publication title -
international journal of engineering and advanced technology
Language(s) - English
Resource type - Journals
ISSN - 2249-8958
DOI - 10.35940/ijeat.b4523.129219
Subject(s) - discrete cosine transform , computer science , codec , field programmable gate array , control reconfiguration , embedded system , computer architecture , scalability , hardware acceleration , computer hardware , video decoder , decoding methods , image (mathematics) , algorithm , artificial intelligence , database
Programmable architectures like GPU based embedded system for video and imaging applications are widely used due to their high performance, as they allow flexibility for running customized functions. However these architectures do not allow reconfiguration of the architecture at run time and optimization of the hardware resources. This paper explores the FPGA based architecture suitable for all video CODEC standards used in multimedia applications which is both programmable and reconfigurable. The proposed architecture demonstrates an accelerator to perform two dimensional 8*8 discrete Cosine Transform (DCT) and Inverse Discrete Cosine Transform (IDCT). The accelerator can be reconfigured to compute higher order two-dimensional DCT/IDCT according to different system requirements and is implemented on Xilinx Zynq evaluation board 7vx485tffg1157-1. The architecture is found to have a high scalability in terms of power and area. The synthesis results reads, 48% improvement in both dynamic and static power consumption, with optimal hardware utilization suitable for high performance video CODECs.