Open AccessApplication of PODEM Algorithm for Fault Detection and Location in FinFet based Combinational VLSI Circuits
Author(s) -
K. V. B. V. Rayudu,
D R Jahagirdar,
Patri Srihari Rao,
Nit Warangal Professor
Publication year - 2019
Publication title -
international journal of engineering and advanced technology
Language(s) - English
Resource type - Journals
ISSN - 2249-8958
DOI - 10.35940/ijeat.b3565.129219
Subject(s) - combinational logic , very large scale integration , spice , fault (geology) , computer science , electronic circuit , fault detection and isolation , algorithm , stuck at fault , automatic test pattern generation , transistor , computer engineering , electronic engineering , logic gate , engineering , embedded system , electrical engineering , artificial intelligence , voltage , seismology , geology , actuator
FinFet transistors are used in major semiconductor organizations and a significant role is played by it in developing the silicon industries. Due to few embedded memories and other circuit issues the transistors have specific faults in manufacturing, designing of the circuit etc. This paper presents an advanced test algorithm to diagnose those faults. The circuit with different gates is designed to identify the places having faults. In addition, different algorithms such as PODEM (Path Oriented Decision Making algorithms) are used to find the fault detection and location. The Furthermore, more complicated circuits are analyzed for fault detection with different approach. In this research work Combinational Circuits are designed using 20nm/32nm technology nodes in LT Spice environment and PODEM Algorithm is implemented which is developed in MATLAB, to detect and identify fault location and sensitive test vector to detect fault in the circuit and results are presented..