Open AccessDesign and Implementation of 256 Bit Modified Square Root Carry Select Adder for Area and Delay Reduction
Author(s) -
Agnes Shiny Rachel,
G Rajakumar.
Publication year - 2019
Publication title -
international journal of engineering and advanced technology
Language(s) - English
Resource type - Journals
ISSN - 2249-8958
DOI - 10.35940/ijeat.b3271.129219
Subject(s) - adder , computer science , reduction (mathematics) , square root , carry (investment) , arithmetic , block (permutation group theory) , scope (computer science) , computer engineering , bit (key) , root (linguistics) , carry save adder , computer hardware , algorithm , telecommunications , mathematics , computer network , linguistics , philosophy , geometry , finance , economics , programming language , latency (audio)
This paper models the behaviour of modified Square Root Carry Select Adder and goes deep to investigate on its scope of reducing area and delay. This helps to overcome the drawback of conventional RCA by performing operations simultaneously for both Cin = 0 and Cin = 1, and the output is multiplexed to obtain the desired response. The work explores opportunities to reduce the area with introduction of BEC logic instead of second block RCA. The implementation of a 4 bit MCSLA and its capability of extending its word size to 8, 16, 32, 64, 128 and 256 bits are presented. The experimental result helps to verify the effectiveness of the approach. This provides understanding on how the reduction of area can bring vital improvements in Very Large Scale Integration.