Open Access2D and 3D Based Network on Chip for a Stream of Data using Label Switching Technique
Author(s) -
N. Mamatha,
S. Sridevi,
G. Indumathi,
K Venkateswaran
Publication year - 2019
Publication title -
international journal of engineering and advanced technology
Language(s) - English
Resource type - Journals
ISSN - 2249-8958
DOI - 10.35940/ijeat.a9407.109119
Subject(s) - interconnection , computer science , network on a chip , embedded system , reduction (mathematics) , power consumption , chip , latency (audio) , computer hardware , power (physics) , computer network , telecommunications , physics , geometry , mathematics , quantum mechanics
Universal interconnection networks are prime performance tailback for high performance SoCs (Systems-on-Chip). Since shrinking the size of the ICs (Integrated Circuits) is the main aim, NoC (Network-on-Chip), being a segmental and mountable design tactic is a propitious substitute to outmoded bus-mode architectures. NoC combined with 3D-Routers and label switching technique can guarantee low power consumption, QoS along with less latency. In the proposed work, 3D NoCs are proven to be more advantageous by achieving 39.9% reduction in Area, 1.7% reduction in Power Consumption, and 11.3% reduction in Memory usage.