Open AccessClock Delayed Dual Keeper Domino Logic Design with Reduced Switching
Author(s) -
A. Varghese,
S R Anusha,
A. Anita Angeline,
V. S. Kanchana Bhaaskaran
Publication year - 2019
Publication title -
international journal of engineering and advanced technology
Language(s) - English
Resource type - Journals
ISSN - 2249-8958
DOI - 10.35940/ijeat.a1072.1291s319
Subject(s) - domino logic , domino , computer science , cadence , logic family , logic optimization , logic level , robustness (evolution) , pass transistor logic , node (physics) , logic synthesis , dual (grammatical number) , reduction (mathematics) , logic gate , electronic engineering , computer hardware , electrical engineering , voltage , transistor , engineering , mathematics , algorithm , chemistry , structural engineering , biochemistry , geometry , catalysis , gene , art , literature
Clock Delayed Dual Keeper domino logic style with Static Switching mechanism (CDDK_SS) using delayed enabling of the keeper circuit and modified discharge path has been proposed in this paper. In CDDK domino circuit, the principle of delayed enabling of keeper circuit offers reduced contention between keeper circuit and Pull Down Network (PDN). The modified discharge path at the output node eradicates the switching at the output node for identical TRUE inputs during the pre-charge phase. This facilitates in obtaining static like output in contrast with conventional domino logic. The simulation results of Arithmetic and Logic Unit (ALU) subsystems demonstrate 17.7% reduction in dynamic power consumption while compared to conventional domino logic. Furthermore, 62% enhancement in speed performance has been achieved with good robustness. Design and simulation have been executed using Cadence® Virtuoso, with UMC 90nm technology node library.