Open AccessArchitectural Enhancement of Network on Chip
Author(s) -
Senthil Athiban,
Mehazin Shaju,
Sravini,
Dr.S Ananiah Durai
Publication year - 2019
Publication title -
international journal of engineering and advanced technology
Language(s) - English
Resource type - Journals
ISSN - 2249-8958
DOI - 10.35940/ijeat.a1054.1291s319
Subject(s) - computer science , architecture , data transmission , computer architecture , chip , transmission (telecommunications) , throughput , transmission rate , embedded system , network on a chip , computer hardware , telecommunications , wireless , art , visual arts
This paper gives a new architectural design suggestion of NoC, with efficient way of communication. Firstly, to create a serial data communication architecture in competence with the existing widely used parallel form of data transmission and reception [1]. Secondly to enable simultaneous transmission and reception between more than one module at the same time. Thirdly to create the architecture that is modifiable as per the need of user. The theoretical data rate calculated was 300 MBps. The throughput we achieved after the completion is 250MBps.