Open AccessMerged Floating Point Multipliers
Author(s) -
Mrudula Singamsetti,
Sadulla Shaik,
Pitchaiah Telagathoti
Publication year - 2019
Publication title -
international journal of engineering and advanced technology
Language(s) - English
Resource type - Journals
ISSN - 2249-8958
DOI - 10.35940/ijeat.a1042.1291s52019
Subject(s) - floating point , multiplier (economics) , computer science , computation , digital signal processing , field programmable gate array , speedup , parallel computing , block (permutation group theory) , computational science , computer hardware , computer architecture , algorithm , mathematics , geometry , economics , macroeconomics
Floating point multipliers are extensively used in many scientific and signal processing computations, due to high speed and memory requirements of IEEE-754 floating point multipliers which prevents its implementation in many systems because of fast computations. Hence floating point multipliers became one of the research criteria. This research aims to design a new floating point multiplier that occupies less area, low power dissipation and reduces computational time (more speed) when compared to the conventional architectures. After an extensive literature survey, new architecture was recognized i.e, resource sharing Karatsuba –Ofman algorithm which occupies less area, power and increasing speed. The design was implemented in mat lab using DSP block sets, simulator tool is Xilinx Vivado.