Open AccessEfficient Hard Decision Fault Diagnosis using Scan Based Testing in Sequential Circuits
Author(s) -
Selvaraj Vimalraj,
E. Nandhakumar,
V. S. Sanjanadevi,
C. Sakthivel
Publication year - 2019
Publication title -
international journal of engineering and advanced technology
Language(s) - English
Resource type - Journals
ISSN - 2249-8958
DOI - 10.35940/ijeat.a1019.1291s619
Subject(s) - checksum , computer science , fault coverage , digital electronics , overhead (engineering) , electronic circuit , algorithm , sequential logic , fault detection and isolation , stuck at fault , set (abstract data type) , power consumption , combinational logic , fault (geology) , error detection and correction , test set , computer engineering , logic gate , power (physics) , engineering , artificial intelligence , physics , electrical engineering , quantum mechanics , seismology , geology , actuator , programming language , operating system
Testing in sequential circuits is extremely difficult because behavior of sequential circuits depends on both the present and past value. Nowadays, in memory applications even single bit changes in digital circuits results in serious error. This paper presents a fault-detection method for difference-set test patterns with efficient hard decision algorithm using majority logic decoder/detector. This algorithm has the ability to correct large number of faults. The proposed checksum method for fault detection and correction significantly reduces testing time. This technique doesn’t require appending parity bits, which makes the area overhead minimal and keeps the extra power consumption low.