Open AccessDynamic activation of power-gating-switch configuration for highly reliable nonvolatile large-scale integrated circuits
Author(s) -
Fangcen Zhong,
Masanori Natsui,
Takahiro Hanyu
Publication year - 2021
Publication title -
japanese journal of applied physics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.487
H-Index - 129
eISSN - 1347-4065
pISSN - 0021-4922
DOI - 10.35848/1347-4065/ac461a
Subject(s) - inrush current , power gating , power (physics) , computer science , voltage , electrical engineering , electronic circuit , non volatile memory , spin transfer torque , tunnel magnetoresistance , electronic engineering , materials science , engineering , physics , transistor , magnetization , nanotechnology , quantum mechanics , layer (electronics) , magnetic field , transformer
Nonvolatile large-scale integrated circuits (NV-LSIs) with a power-gating (PG) technique can drastically reduce the wasted static power consumption, which is an attractive feature in Internet-of-Things (IoT) edge devices. However, the issues of inrush current and voltage fluctuation due to PG-state transitions are preventing their advancement. This paper describes a technique for stabilizing the operation of NV-LSIs during PG by minimizing inrush current effects and voltage fluctuations. In the proposed technique, several PG switch configurations are prepared and one of them are dynamically selected in accordance with the expected operation conditions, which could minimize inrush current and voltage fluctuations in the power supply. This technique is applied to sub-array-level PG of a spin-transfer torque magneto-resistive random-access memory (STT-MRAM). As a result, inrush current level and the recovery time of the power supply from a sleep state are reduced by up to 83.8% and 68.7%, respectively, while satisfying given performance requirements.