Open AccessNormally-off sputtered-MoS2 nMISFETs with TiN top-gate electrode all defined by optical lithography for chip-level integration
Author(s) -
Kentaro Matsuura,
Masahiko Hamada,
Tomoyo Hamada,
Haruki Tanigawa,
Takumi Sakamoto,
Atsushi Hori,
Iriya Muneta,
Takamasa Kawanago,
Kuniyuki Kakushima,
Kazuo Tsutsui,
Atsushi Ogura,
Hitoshi Wakabayashi
Publication year - 2020
Publication title -
japanese journal of applied physics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.487
H-Index - 129
eISSN - 1347-4065
pISSN - 0021-4922
DOI - 10.35848/1347-4065/aba9a3
Subject(s) - materials science , optoelectronics , annealing (glass) , electrode , titanium nitride , lithography , photolithography , nitride , dielectric , threshold voltage , tin , transistor , nanotechnology , voltage , layer (electronics) , electrical engineering , chemistry , metallurgy , engineering
We demonstrate chip-level integrated n -type metal–insulator–semiconductor field effect transistors with a sputtered molybdenum disulfide (MoS 2 ) thin channel and titanium nitride top-gate electrode, all defined by optical lithography. The devices successfully exhibit a normally-off operation and the highest off-voltage. This is achieved by the single dielectric layer and forming gas annealing, which reduce the positive fixed charges in aluminum oxide (Al 2 O 3 ) film and interface trap densities between the MoS 2 and Al 2 O 3 films, respectively. These normally-off MISFETs are suitable for internet-of-things edge devices with low energy consumption using two-dimensional materials in the future.