
DESIGN OF SHARED BUFFER ARCHITECTURE FOR CPU-GPU ON CHIP NETWORK
Author(s) -
Deepika Pitliya,
Namita Palecha
Publication year - 2020
Publication title -
international journal of electrical engineering and technology
Language(s) - English
Resource type - Journals
eISSN - 0976-6553
pISSN - 0976-6545
DOI - 10.34218/ijeet.11.4.2020.041
Subject(s) - computer science , buffer (optical fiber) , parallel computing , architecture , computer architecture , embedded system , chip , computer hardware , operating system , telecommunications , art , visual arts