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A NOVEL APPROACH FOR POWER OPTIMIZATION IN SEQUENTIAL CIRCUITS USING LATCH BASED CLOCK GATING
Author(s) -
S Kavya,
B. S. Kariyappa
Publication year - 2020
Publication title -
international journal of electrical engineering and technology
Language(s) - English
Resource type - Journals
eISSN - 0976-6553
pISSN - 0976-6545
DOI - 10.34218/ijeet.11.4.2020.039
Subject(s) - clock gating , computer science , electronic circuit , power gating , power (physics) , gating , power optimization , electronic engineering , parallel computing , clock skew , clock signal , electrical engineering , engineering , transistor , physics , voltage , power consumption , quantum mechanics , physiology , biology

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