Open AccessDESIGN OF LOW POWER HIGH SPEED ERROR TOLERANT ADDERS USING FPGA
Author(s) -
Libya Thomas
Publication year - 2019
Publication title -
international journal of advanced research in engineering and technology
Language(s) - English
Resource type - Journals
eISSN - 0976-6499
pISSN - 0976-6480
DOI - 10.34218/ijaret.10.1.2019.009
Subject(s) - adder , field programmable gate array , computer science , power (physics) , computer hardware , embedded system , parallel computing , telecommunications , physics , latency (audio) , quantum mechanics