Open AccessLAYOUT DESIGN OF 4-BIT RIPPLE CARRY ADDER BASED ON PASS TRANSISTOR LOGIC
Author(s) -
Alexey Gnilenko
Publication year - 2020
Publication title -
sistemnì tehnologìï
Language(s) - English
Resource type - Journals
eISSN - 2707-7977
pISSN - 1562-9945
DOI - 10.34185/1562-9945-1-126-2020-05
Subject(s) - adder , computer science , carry save adder , serial binary adder , electronic engineering , multiplexer , 4 bit , computer hardware , microprocessor , logic gate , transistor , carry (investment) , arithmetic , electrical engineering , cmos , multiplexing , engineering , mathematics , algorithm , telecommunications , voltage , finance , economics
The full adder is a key element of any arithmetic logic units used in microprocessor systems. For microprocessor components created for modern mobile digital devices, compact layout design on the silicone chip is of great importance. In this paper an area effective layout design on the chip is proposed for 4-bit ripple carry adder based on pass transistor logic. The full adder is simulated using EDA tool and output signal waveforms are obtained to demonstrate the functionality of the design. It is shown that 1-bit full adder based on pass transistor logic and composed of two 3T XOR gates and one 2T multiplexer allows us to obtain area effective layout design on the chip for 4-bit ripple carry adder providing acceptable characteristics for output signals.