A REVIEW OF LOW VOLTAGE AND LOW POWER CMOS ADDERS USING VLSI DESIGN IN VERILOG/VHDL

The dominant portion of power dissipation inCMOS adder circuits, due to logic transitions, varies as thesquare of the supply, significant savings in powerdissipation may be exacted by operating with reducedsupply voltage. If the supply voltage is reduced whilethreshold voltage stays same, the noise margins willreduce. Addition is a crucial process because it usuallyinvolve carry ripple steps which must propagate a carrysignal from each bit to it’s higher bit position. This resultsin a substantial circuit delay. The adder which lies in thecrucial delay path will effectively determine the systemoverall speed. To improve noise margins, the thresholdvoltages must also be made smaller. However subthreshold leakage current increases exponentially whenthreshold voltage is reduced. The higher static dissipationmay then offset the reduction in transitions portion of thedissipation. Hence the devices needed to have thresholdvoltages that maximizes the net reduction in thedissipation. Addition is an obligatory operation that iscrucial to processing the fundamental arithmeticoperations. Due to the potential versatility of adders in thiscontemporary research field, the existing adders andadder designs currently intended for future low voltageand low power environments. This can be achieved by theCMOS adders namely Parallel Adder, Ripple CarryAdder(RCA), Carry Look Ahead Adder(CLA), CarrySelect Adder(CSL), Carry Save Adder(CSA), Carry SkipAdder(CSK), Conditional Sum Adder(COS).