Open AccessHALF ADDER DESIGN USING VARIOUS TECHNOLOGIES AND COMPARISON OF
Author(s) -
Rituraj Yadav,
Ashish Sura,
Sunita Dahiya
Publication year - 2021
Publication title -
international journal of engineering applied science and technology
Language(s) - English
Resource type - Journals
ISSN - 2455-2143
DOI - 10.33564/ijeast.2021.v06i02.016
Subject(s) - adder , serial binary adder , computer science , cmos , nmos logic , electronic engineering , circuit design , power–delay product , logic gate , transistor , arithmetic , electrical engineering , engineering , mathematics , embedded system , algorithm , voltage
: In this paper, investigate and analysis varioustechniques for implementing a half adder circuit withthe fewest transistors possible. In digital electronics halfadder combinational circuit used to add two numbers.It is an arithmetic circuit that performs the arithmeticoperation of adding two single-bit words. The halfadder technique, design of half adder using AVLtechnology, Design of a 3-T Half Adder, NMOS passtransistors logic design of half adder using 2:1 MUX,half adder circuit design with CMOS NAND gates, halfadder circuit design with CMOS transmission logicgates in cadence virtuoso. In this section, compare halfadder circuit design techniques and compare variousparameters of half adder circuit design used variouscircuit design techniques. Conventional techniquesrequired fewer number routing resources. A 3-T halfadder circuit performs with less delay, high speed,small layout area, less power consumption and batterefficiency and accuracy