Open AccessFPGA IMPLEMENTATION OF FIR FILTER ARCHITECTURE BASED ON FIXED WIDTH BOOTH MULTIPLIER WITH SIGN-DIGIT BASED CONDITIONAL PROBABILITY ESTIMATION
Author(s) -
B V Arpitha,
L R Meenakshi
Publication year - 2019
Publication title -
international journal of engineering applied science and technology
Language(s) - English
Resource type - Journals
ISSN - 2455-2143
DOI - 10.33564/ijeast.2019.v04i03.084
Subject(s) - finite impulse response , multiplier (economics) , field programmable gate array , booth's multiplication algorithm , sign (mathematics) , arithmetic , filter (signal processing) , numerical digit , mathematics , computer science , algorithm , speech recognition , computer hardware , computer vision , adder , telecommunications , mathematical analysis , economics , macroeconomics , latency (audio)
Digital Filters are intensively used in all DSP sub-systems and they are said to be the most important component of any DSP applications. Therefore large number of research has been carried out on designing such filters. Reduced power consumption and area optimization are the most important considerations that have to be taken care of while designing filters. Adders, Flip-Flops and Multipliers are the major blocks of Finite Impulse Response (FIR) Filter, Where multiplier is the major part and the performance of Filter depends on it. In this Paper fixed width booth multiplier with sign-digit-based conditional probability estimation is used in filter architecture. Booth-encoded Sign-digit-based Conditional Probability Estimation (BSCP) multiplier optimizes the area and power consumption by reducing the partial products and using compensation circuits. The proposed FIR filter architecture is designed using Verilog HDL and synthesis is done in Xilinx ISE Design tool, simulation results are verified in Modelsim and implemented on FPGA Spartan 3 XC3S200TQ144-4 device. Keywords— FIR Filter, Modified Booth Encoding, BSCP Multiplier, Impulse Response, FPGA