Open Access2 Efficient AES-XTS Pipelined Implementation on FPGA
Author(s) -
Shakil Ahmed,
Muhammad Akram Naseem
Publication year - 2014
Publication title -
sir syed university research journal of engineering and technology
Language(s) - English
Resource type - Journals
eISSN - 2415-2048
pISSN - 1997-0641
DOI - 10.33317/ssurj.v1i1.56
Subject(s) - field programmable gate array , encryption , computer science , advanced encryption standard , throughput , embedded system , block cipher mode of operation , aes implementations , computer hardware , computer network , operating system , wireless , computer security
In past years, it has been considered that only datacommunicated via networks need to be secured. This paradigmnow shifted towards securing data at rest. With its increasingsignificance, IEEE has introduced a mode of AdvancedEncryption Standard (AES) named as XTS-AES. Few of itsimplementations exist. This paper presents a high throughputand highly efficient fully unrolled pipelined design of AES-XTSon FPGA. The proposed implementation incorporates only oneAES core for both tweak value encryption as well as dataencryption. Further our proposed design calculates tweak valuein parallel to data encryption/decryption process. The resultshave achieved a throughput of 35.8 Gbps with an efficiency of 8.4Mbps/slice. This design offers the best result forThroughput/Area that is 4.641 Mbps/area.