Open AccessSignificance-Driven Logic Compression for Energy Efficient Multiplier Design
Author(s) -
Sonal Sindhu,
K Spoorthy,
K M Suchitha,
K Y Annapurna
Publication year - 2020
Publication title -
asian journal of convergence in technology
Language(s) - Uncategorized
Resource type - Journals
ISSN - 2350-1146
DOI - 10.33130/ajct.2020v06i02.001
Subject(s) - adder , multiplier (economics) , computer science , arithmetic , transistor count , transistor , power–delay product , logic gate , pass transistor logic , electronic engineering , algorithm , mathematics , voltage , electrical engineering , cmos , engineering , economics , macroeconomics