Open AccessSeven-Level Symmetrical Series/Parallel Multilevel Inverter with PWM Technique Using Digital Logic
Author(s) -
Nagaraju Motaparthi,
M. Kiran Kumar
Publication year - 2021
Publication title -
international journal of electrical and computer engineering systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.141
H-Index - 4
eISSN - 1847-7003
pISSN - 1847-6996
DOI - 10.32985/ijeces.12.3.1
Subject(s) - pulse width modulation , total harmonic distortion , topology (electrical circuits) , voltage , inverter , series and parallel circuits , computer science , series (stratigraphy) , electronic engineering , matlab , control logic , h bridge , electrical engineering , engineering , computer hardware , paleontology , biology , operating system
This paper attempts to come up with a proposed configuration of Multilevel inverters with a lesser number of switches that are smaller in size, lesser in cost and with a higher efficiency. Designing an inverter topology with a lesser number of switches and proper control technique is the major challenge. cascaded H-Bridge (CHB) topology are more popular among the existing configurations of multilevel inverters (MLI). Even though it can produce more levels, it needs to accommodate a huge number of switches for higher levels. The focus of this paper is to reduce the number of components for the same voltage level of cascaded H- Bridge configuration. In addition to that, generating the gating pulses for the switches is difficult when there is an asymmetry in the switches. A new symmetrical series/parallel configuration is proposed with reduced switch count and the pulse width modulation (PWM) technique is implemented with digital logic to generate the required gating pulses for the switches. The total harmonic distortion (THDI) of the output current is reduced with this PWM technique. The simulation has been carried out in MATLAB/Simulink software for both R (resistive) and R-L (resistive -inductive) loads.