Open AccessTHE SUBSYSTEM OF HARDWARE ACCELERATION OF TEXT CLASSIFICATION IN THE FPGA BASIS
Author(s) -
Tetiana Golub,
Irina Zeleneva,
Svitlana Hrushko,
M.A. Pavlishyn
Publication year - 2020
Publication title -
včenì zapiski tavrìjsʹkogo nacìonalʹnogo unìversitetu ìmenì v. ì. vernadsʹkogo. serìâ tehnìčnì nauki
Language(s) - English
Resource type - Journals
eISSN - 2663-595X
pISSN - 2663-5941
DOI - 10.32838/2663-5941/2020.2-1/11
Subject(s) - field programmable gate array , acceleration , computer science , hardware acceleration , basis (linear algebra) , computer hardware , embedded system , physics , mathematics , geometry , classical mechanics