Open AccessDesign and Implementation of High Speed Area Efficient Carry Select Adder Using Spanning Tree Adder Technique
Author(s) -
Hima Bindu Vykuntam,
M.P. Chennaiah,
K. Sudhakar
Publication year - 2018
Publication title -
international journal of scientific research in science and technology
Language(s) - English
Resource type - Journals
eISSN - 2395-602X
pISSN - 2395-6011
DOI - 10.32628/ijsrst184114
Subject(s) - adder , carry save adder , serial binary adder , computer science , parallel computing , arithmetic , carry (investment) , mathematics , telecommunications , finance , economics , latency (audio)
In this paper, we propose Carry Select Adder (CSLA) architecture with parallel prefix adder. Instead of using 4-bit Brent Kung Adder (BKA), another parallel prefix adder i.e., 4-bit spanning Tree (ST) adder is used to design CSA. Because Adders are key element in digital design, which are not only performing addition operation, but also many other function such as subtraction, multiplication and division. A Ripple Carry Adder (RCA) gives the most complicated design as-well-as longer computation time so that we may gone for parallel prefix adders. This time critical application we use Spanning tree parallel prefix adder to drive fast results but they lead to increase in area. Proposed Carry Select Adder understands between RCA and BKA in term of area and delay. Delay of Existing adders is larger therefore we have replaced those with Brent Spanning Tree parallel prefix adder which gives fast result. This paper describes comparative performance of 4-bit RCA and 4-Bit BK parallel prefix adders with Our Proposed Spanning Tree adder based carry select adder designed using Xilinx ISE tool.