
Minimization of Leakage Currents in Dram 4x4 Using SVL Technique
Author(s) -
N. Geetha Rani,
C. Soundarya Lahari,
G. Revathi,
K. Chandrika,
G. Riya
Publication year - 2021
Publication title -
international journal of scientific research in science, engineering and technology
Language(s) - English
Resource type - Journals
eISSN - 2395-1990
pISSN - 2394-4099
DOI - 10.32628/ijsrset218435
Subject(s) - dram , cmos , leakage (economics) , computer science , chip , integrated circuit , dissipation , electronic circuit , electrical engineering , electronics , power (physics) , electronic engineering , embedded system , engineering , computer hardware , physics , quantum mechanics , economics , macroeconomics , thermodynamics
In recent years, due to development of integrated circuits technology, power is being given comparable weight to area and speed considerations. The power consumed for any given function in any complementary metal-oxide-semiconductor (CMOS) circuit must be reduced for either of the two different reasons. One is to reduce heat dissipation in order to allow a large density of functions to be incorporated on an Integrated Circuit (IC) chip. Any amount of power dissipation is worthwhile as long as it does not degrade overall circuit performance. The other reason is to save energy in battery operated instruments like in electronic watches where average power is in microwatts.Low power is the major issue not only in portable devices but also in non-portable devices. So, it is apparent that one has to resolve low power design methodologies for the design of high throughput, low power digital systems. By using this SVL technique using DRAM we are going to reduce the leakage currents and also improves the performance of the circuit.