Open AccessDesign and Construction of 3 x 3 Bits Programmable Logic Array (PLA) Circuit
Author(s) -
Sanda Win,
San San Htwe,
Sandar Win,
Myint Myint Swe
Publication year - 2020
Publication title -
international journal of scientific research in science, engineering and technology
Language(s) - English
Resource type - Journals
eISSN - 2395-1990
pISSN - 2394-4099
DOI - 10.32628/ijsrset207347
Subject(s) - simple programmable logic device , programmable logic array , macrocell array , programmable array logic , programmable logic device , erasable programmable logic device , logic family , logic gate , complex programmable logic device , computer science , sequential logic , logic optimization , logic synthesis , pass transistor logic , programmable logic controller , combinational logic , computer hardware , digital electronics , electronic circuit , algorithm , electrical engineering , engineering , operating system
A programmable logic array (PLA) is a kind of programmable logic device used to implement combinational logic circuits. The PLA has a set of programmable AND gate planes, which link to a set of programmable OR gate planes, which can then be conditionally complemented to produce an output. It has 2N AND gate s for N input variables and for M outputs from PLA, there should be M OR gates, each with programmable inputs from all of the AND gates. This layout allows for many logic functions to be synthesized in the sum of products canonical forms. The Programmable Logic Array (PLA) has a programmable AND array followed by a programmable OR array. Programmable Logic Array (PLA) circuit is built by using AND gates and OR gates. The 3x 4 bits data can be stored in this circuit. The large storage data bits of PLA circuit store by a using large AND-OR array with lots of inputs and product terms, and programmable connections. Programmable Logic Array circuit functions as ROM circuit.