Open AccessLeakage Current Reduction in CMOS Circuits Using Stacking Technique
Author(s) -
N. Geetha Rani,
G. Ragapriya,
Harshitha,
Girada Swetha,
B. Sri Jyothi
Publication year - 2020
Publication title -
international journal of scientific research in science, engineering and technology
Language(s) - English
Resource type - Journals
eISSN - 2395-1990
pISSN - 2394-4099
DOI - 10.32628/ijsrset207344
Subject(s) - transistor , cmos , stacking , leakage (economics) , materials science , electronic circuit , chip , integrated circuit , nanometre , optoelectronics , electronic engineering , leakage power , electrical engineering , nanotechnology , engineering physics , engineering , physics , voltage , nuclear magnetic resonance , economics , composite material , macroeconomics
This paper deals with The rapid progress in semiconductor technology have led the feature sizes of transistor to be shrunk there by evolution of Deep Sub-Micron (DSM) technology. There by the extremely complex functionality is enabled to be integrated on a single chip. So, transistor size is reduced to few nanometers. By reducing the size drastically some problems are occurred. In that leakage power is one of the disadvantage. By using this stacking technique we are going to reduce the leakage currents.