Open AccessReceiver Designs for Electronic Toll Collection Systems : A Survey
Author(s) -
Rarika Ravi,
A.L. de Assis
Publication year - 2020
Publication title -
international journal of scientific research in computer science, engineering and information technology
Language(s) - English
Resource type - Journals
ISSN - 2456-3307
DOI - 10.32628/cseit20623
Subject(s) - cmos , baseband , electronic engineering , chip , dedicated short range communications , electrical engineering , engineering , electronic toll collection , electronic circuit , sensitivity (control systems) , radio frequency , radio receiver design , dynamic range , toll , computer science , wireless , telecommunications , transmitter , channel (broadcasting) , biology , genetics
This paper discusses about different receiver designs adopted so far for various electronic toll collection systems. A comparative analysis based on the discussions is also provided. It shows that each design has it's own advantages and disadvantages compared to others. The main aim of this paper is to identify the most suitable design. The researches shows that the receiver design described in the 5.8GHz digitally controlled DSRC receiver for Chinese electronic toll collection system is the most suitable one. Here all RF, IF blocks and digital baseband for on-chip automatic gain control, are integrated on an RF-SoC. The proposed digitally controlled LNA and mixer circuits are elaborated. The technology used is 0.13μm CMOS technology. The RF block occupies a chip area of 0.75mm2. It consumes 22mA under a 1.5V supply voltage. The bit error rate maintains better than 10-6, the input power level varies from -75dBm to -8dBm. This design provides a receiver sensitivity improvement of at least 25%, and a dynamic range enhancement of at least 12%.