Open AccessAutomatic chip testing system
Author(s) -
Trang Thi Thu Tran,
Phuoc-Loc Diep,
Vu-Huynh-Tuan Phan,
Thuy Ngoc Nguyen,
Trung-Khanh Le,
Quoc-Hung Huynh,
Duc-Hung Le
Publication year - 2020
Publication title -
khoa học và công nghệ: tự nhiên
Language(s) - English
Resource type - Journals
ISSN - 2588-106X
DOI - 10.32508/stdjns.v3i3.605
Subject(s) - universal asynchronous receiver/transmitter , computer science , embedded system , asynchronous communication , software , interface (matter) , computer hardware , process (computing) , chip , system on a chip , operating system , computer network , telecommunications , bubble , maximum bubble pressure method
In this paper, we implement an automatic chip testing system which can be applied on various types of chip packages. The conventional systems, such as manual chip testing systems, often repeat the same steps for input conditions; or high-cost testing systems are designed to be highly optimized, but the installation and operating costs are very expensive. This makes these systems difficult to be applied in education, research or small companies. The automatic chip testing system overcomes the above two weaknesses. The proposed system not only meets the requirement of a basic chip testing process, but also operates automatically and reduces the cost. Users only need to provide input data via a Graphical User Interface (GUI) which is built using C# programming language, then the system will automatically operate and return the corresponding output data to the software to synthesize and compare with the user’s expected data. The hardware is built on the TR4 FPGA Development Kit which helps save the cost of hardware design and its resources. The software and hardware withcommunicate to each other via Universal Asynchronous Receiver-Transmitter (UART) protocol. The proposed system is automatic, optimized and low-cost so that it can be applied both in IC design education and industry.