Open AccessAn efficient floating-point FFT twiddle factor implementation based on adaptive angle recoding CORDIC algorithm
Author(s) -
Thao Thi Phuong Vo,
Quynh Thi Nhu Truong,
Thuc Trong Hoang,
Hung Duc Le
Publication year - 2017
Publication title -
khoa học và công nghệ: tự nhiên
Language(s) - English
Resource type - Journals
ISSN - 2588-106X
DOI - 10.32508/stdjns.v1it4.468
Subject(s) - cordic , stratix , twiddle factor , fast fourier transform , field programmable gate array , computer science , throughput , algorithm , factor (programming language) , floating point , parallel computing , computer hardware , mathematics , fourier transform , fourier analysis , mathematical analysis , short time fourier transform , telecommunications , wireless , programming language
In this paper, a single-precision floating-point FFT twiddle factor (TF) implementation is proposed. The architecture is based on the Adaptive Angle Recoding CORDIC (AARC) algorithm. The TF design was built and verified on Altera Stratix IV FPGA chip and 65nm SOTB synthesis. The FPGA implementation had 103.9 MHz maximum frequency, throughput result of 16.966 Mega-Sample per second (MSps), and resources utilization of 7.747 ALUTs and 625 registers. On the other hand, the SOTB synthesis has 16.858 standard cells on an area of 298x291 μm2, 166 MHz maximum frequency, and the speed of 27.107 MSps. The accuracy results were 1.133E-10 Mean-Square-Error (MSE) and about 26 part-per-million (ppm) maximum error.