DESIGNING A SOPC FOR FACE RECOGNITION USING WMPCA ALGORITHM | Zendy

Nhu Truong | Zendy; Thi Diem Tran | Zendy

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DESIGNING A SOPC FOR FACE RECOGNITION USING WMPCA ALGORITHM

Author(s) -

Nhu Truong,

Thi Diem Tran

Publication year - 2011

Publication title -

science and technology development journal

Language(s) - English

Resource type - Journals

ISSN - 1859-0128

DOI - 10.32508/stdj.v14i4.2033

Subject(s) - modular design , field programmable gate array , computer science , principal component analysis , component (thermodynamics) , embedded system , chip , system on a chip , computer hardware , vector quantization , hardware acceleration , facial recognition system , computer architecture , pattern recognition (psychology) , algorithm , artificial intelligence , operating system , telecommunications , physics , thermodynamics

A flexible accelerator hardware for full-search vector quantization (VQ) has been developed as a component for a system on a programmable chip (SoPC) to use in real-time image compression and recognition applications. Nowadays, FPGA and its SoPC (System on Programmable Chip) tools are powerful enough to efficiently develop a flexible hardware accelerator for VQ application. In addition, one of statistical analysis methods, weighted modular principal component analysis, has showed efficiencies in recognition applications. In this paper, a parallel architecture for online face recognition using weighted modular principal component analysis (WMPCA) and its system-on-programmable-chip (SoPC) implementation are discussed.

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