Open AccessPAID – A NOVEL FRAMEWORK FOR DESIGN AND SIMULATION OF ASYNCHRONOUS CIRCUITS
Author(s) -
Vu Duc Anh Dinh
Publication year - 2011
Publication title -
khoa học công nghệ
Language(s) - English
Resource type - Journals
ISSN - 1859-0128
DOI - 10.32508/stdj.v14i2.1907
Subject(s) - netlist , asynchronous communication , computer science , asynchronous system , asynchronous circuit , electronic circuit , synchronizer , clock signal , computer architecture , electronic engineering , embedded system , synchronous circuit , electrical engineering , engineering , distributed computing , jitter , telecommunications
Contrary to the synchronous circuits, the asynchronous circuits operate with a mechanism of local synchronization (without clock signal). For many years, they showed their relevance with respect to the synchronous circuits thanks to their properties of robustness, low power, low noise and modularity. However, the lack of design methods and associated tools prevents them from being widely spread. This paper deals with a new design methodology for integrated asynchronous circuits and EDA tools. The suggested design method allows on one hand to model circuits in a highlevel language, and on the other hand to generate circuits using only elementary logical gates and Muller gates. This method was prototyped by the development of an EDA design tool for asynchronous circuits. The combination of design methodologies and supporting tools creates a design framework for asynchronous circuits, namely PAiD ("Project of Asynchronous Circuit Design"). This framework allows compilation and synthesis of circuits, described by high-level language ADL ("Asynchronous Description Language"), to generate asynchronous circuits. The result of the synthesizer is a functional netlist of the circuits. This netlist can be then mapped to a specific-technology gate library for asynchronous circuits. During the design process, the circuit can be tested through the simulation process in different levels of abstraction.