Open AccessA Low Power, Leakage Reduction, High Speed 8-Bit Ripple Carry TSPC Adder using MTCMOS Dynamic Logic
Author(s) -
Bhukya Shankar,
Ravikanth Sivangi
Publication year - 2016
Publication title -
cvr journal of science and technology/cvr journal of science and technology
Language(s) - English
Resource type - Journals
eISSN - 2581-7957
pISSN - 2277-3916
DOI - 10.32377/cvrjst1008
Subject(s) - adder , leakage power , dynamic demand , computer science , reduction (mathematics) , ripple , carry (investment) , leakage (economics) , bit (key) , pass transistor logic , power (physics) , logic gate , logic level , electronic engineering , arithmetic , parallel computing , cmos , electrical engineering , engineering , algorithm , electronic circuit , mathematics , digital electronics , transistor , physics , computer network , macroeconomics , geometry , quantum mechanics , finance , economics , voltage