Open AccessEfficient Place and Routing CAD Techniques for the Reduction of Power Dissipation in FPGAs
Author(s) -
M.V. Sushumna
Publication year - 2016
Publication title -
cvr journal of science and technology
Language(s) - English
Resource type - Journals
eISSN - 2581-7957
pISSN - 2277-3916
DOI - 10.32377/cvrjst1004
Subject(s) - field programmable gate array , computer science , schematic , logic block , cad , routing (electronic design automation) , embedded system , idle , reduction (mathematics) , power (physics) , computer hardware , dissipation , reconfigurable computing , power optimization , logic synthesis , logic gate , algorithm , electronic engineering , engineering , physics , geometry , mathematics , quantum mechanics , engineering drawing , thermodynamics , power consumption , operating system
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