Open AccessDesign of Fast Locking ADPLL via FFC Technique using VHDL-AMS
Author(s) -
R. Bhavani
Publication year - 2016
Publication title -
cvr journal of science and technology
Language(s) - English
Resource type - Journals
eISSN - 2581-7957
pISSN - 2277-3916
DOI - 10.32377/cvrjst1003
Subject(s) - vhdl , spice , computer science , verilog , vhdl ams , electronic engineering , phase locked loop , embedded system , hardware description language , engineering , field programmable gate array , jitter
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