
Hazards and Glitch Power Reduction of CMOS Full Adder in 90nm Technology
Author(s) -
Birinderjit Singh
Publication year - 2014
Publication title -
cvr journal of science and technology/cvr journal of science and technology
Language(s) - English
Resource type - Journals
eISSN - 2581-7957
pISSN - 2277-3916
DOI - 10.32377/cvrjst0607
Subject(s) - glitch , cmos , adder , reduction (mathematics) , power (physics) , computer science , electronic engineering , embedded system , electrical engineering , engineering , mathematics , physics , geometry , quantum mechanics